CPLD

CPLD Overview

Complex programmable logic devices are the programmable integrated circuits or microchips. CPLDs are an enhanced type of PLDs. The designers can configure CPLDs through programming. CPLDs are designed to implement digital hardware such as mobile phones. Mostly CPLDs are used in embedded systems design and development.

CPLD logic Blocks

CPLDs consist of number of logic block. One block contains eight to sixteen macrocells. These macrocells within the block are interconnected. Various logic blocks can be programmed to implement a specific function. The blocks may also be connected depending upon the requirements.

CPLD Logic Gates

The macrocells in CPLDs contain sum of product combinational logic functions. One macrocell can contain four to sixteen product terms. These product terms are basically the AND gates whereas sum means OR gate function. Macrocells may also contain a flip-flop or shift registers to implement sequential logic. Besides sum of product expressions a CPLD may contain complex feedback paths between macrocells. CPLDs also implement integer arithmetic for commonly used functions. This allows more flexibility in the design implementation. Different CPLDs contain different number of logic gates and shift registers. CPLDs contain logic gates ranging between thousands to tens of thousands. This large number of gate availability allows the designers to implement complex data processing devices.

CPLD Specifications

Supply voltage, power dissipation, operating current, and stand by current vary for various CPLDs. CPLDs also vary in logic families and IC packaging. Memory choices include ROM, RAM, CAM (content addressable memory), FIFO (first in first out), and LIFO (last in last out) memories. Memory size is also different among CPLDs. Usually CPLDs memories are of bits or megabit sizes.

CPLD Performance Specifications

Performance specifications of a CPLD include internal frequency, propagation delay, and speed grade. Internal frequency is specified by the speed at which a CPLD transfers data internally. Propagation delay is the time period an input takes to reach at output in the logic circuit. Speed grade is the delay of macrocell. It is expressed in nanoseconds. A CPLD having speed grade of –10 nanoseconds means that it has the delay of 10 nanoseconds through the macrocell. Higher the device speed grade lower slower will be the device and vice versa.

CPLD Timing Characteristics

Timing characteristics of a complex programmable logic device (CPLD) are predictable. Therefore CPLDs are quite suitable for critical, high performance, and control applications. Also the timing delay of CPLDs is shorter than other programmable logic devices, especially FPGAs.

CPLD Applications

CPLD offer larger design capacity that SPLDs but lesser logic capability than FPGAs. CPLDs require small amount of power and also less expansive than other programmable devices. This is what makes them suitable for cost sensitive and battery operated portable applications. Moreover often CPLDs are used for simple applications like address decoding.

CPLDs and SoC design

Designers often use CPLD for a System On Chip (SoC) Design. The reason is its integrated phase locked loops (PLLs) and delay locked loops (DLLs). PLL and DLL clock multiplication produces a high-speed internal clock. The clock frequency is manually controllable. Control over frequency is quite critical for system integration as various components function at different frequency. Moreover Clock is useful for data sampling in DSP (digital signal processing).